RISC-V: KVM: Don't add SBI multi regs in get-reg-list
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 13 Dec 2023 17:09:53 +0000 (18:09 +0100)
committerAnup Patel <anup@brainfault.org>
Fri, 29 Dec 2023 07:01:40 +0000 (12:31 +0530)
commit7f58de96aa5e871dd553499e2c84fc801658eab6
treeb135a33f8616ee550ec53644cd541651bebdfc33
parentc19829ba1e4d119e69b1ac9a96d5a0b86f7233e9
RISC-V: KVM: Don't add SBI multi regs in get-reg-list

The multi regs are derived from the single registers. Only list the
single registers in get-reg-list. This also makes the SBI extension
register listing consistent with the ISA extension register listing.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/vcpu_onereg.c