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(parent: fea7d77) | patch
target/sh4: fix FPSCR cause vs flag inversion
authorAurelien Jarno <aurelien@aurel32.net>
Sun, 2 Jul 2017 18:34:55 +0000 (20:34 +0200)
committerAurelien Jarno <aurelien@aurel32.net>
Tue, 18 Jul 2017 21:39:15 +0000 (23:39 +0200)
commit801f4dac57dad6b340ff3f60c5d9b045a2c68a0e
tree5ddd2d1286654b91baad032dd8c1d30c0e65a80ftree | snapshot
parentfea7d77d3ea287d3b1878648f3049fc6bb4fd57bcommit | diff
target/sh4: fix FPSCR cause vs flag inversion

The floating-point status/control register contains cause and flag
bits. The cause bits are set to 0 before executing the instruction,
while the flag bits hold the status of the exception generated after
the field was last cleared.

Message-Id: <20170702202814.27793-4-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target/sh4/op_helper.c diff | blob | history
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