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(parent: 1840518) | patch
clk: imx8mq: Correct the pcie1 sels
authorRichard Zhu <hongxing.zhu@nxp.com>
Mon, 15 Mar 2021 08:17:48 +0000 (16:17 +0800)
committerAbel Vesa <abel.vesa@nxp.com>
Sun, 4 Apr 2021 19:39:05 +0000 (22:39 +0300)
commit8304b15e132f1608973aca4527a8e12af41ddc0e
tree9ad1122ac74a0bb51dd546747d84f2028cc3dbf1tree | snapshot
parent1840518ae7de0e1eeb9075069cbe632fde16c88dcommit | diff
clk: imx8mq: Correct the pcie1 sels

- The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
Change the sys2_pll_500m to sys2_pll_50m.
- Correct one misspell of the imx8mq_pcie1_ctrl_sels definition, from
"sys2_pll_250m" to "sys2_pll_333m".

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
drivers/clk/imx/clk-imx8mq.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git