target/riscv: Adjust csr write mask with XLEN
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Thu, 20 Jan 2022 12:20:37 +0000 (20:20 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 21 Jan 2022 05:52:57 +0000 (15:52 +1000)
commit83b519b8a44d6b7d9b9d9763e7189061e116215d
treea28937805f66159e8e2eb1b10e95e81d437d3367
parent47bdec821b8dda7658e3e802a26b9bd8319cdb49
target/riscv: Adjust csr write mask with XLEN

Write mask is representing the bits we care about.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/op_helper.c