RDMA/mlx5: Fix the flow of a miss in the allocation of a cache ODP MR
authorAharon Landau <aharonl@nvidia.com>
Tue, 15 Feb 2022 17:55:30 +0000 (19:55 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 8 Apr 2022 12:23:34 +0000 (14:23 +0200)
commit847f8677e3677c3750bb213ad3c51227097cecf7
treebc9880a1b82c31218486c0d9d845468367e89c5a
parentc8db786858d895ac58342f67767b4999ae6538fa
RDMA/mlx5: Fix the flow of a miss in the allocation of a cache ODP MR

[ Upstream commit 2f0e60d5e9f96341a0c8a01be8878cdb3b29ff20 ]

When an ODP MR cache entry is empty and trying to allocate it, increment
the ent->miss counter and call to queue_adjust_cache_locked() to verify
the entry is balanced.

Fixes: aad719dcf379 ("RDMA/mlx5: Allow MRs to be created in the cache synchronously")
Link: https://lore.kernel.org/r/09503e295276dcacc92cb1d8aef1ad0961c99dc1.1644947594.git.leonro@nvidia.com
Signed-off-by: Aharon Landau <aharonl@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/infiniband/hw/mlx5/mr.c