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(parent: 5fe60d3) | patch
MIPS: DTS: CI20: Parent MSCMUX clock to MPLL
authorPaul Cercueil <paul@crapouillou.net>
Sun, 4 Jun 2023 14:56:39 +0000 (16:56 +0200)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 9 Jun 2023 07:55:38 +0000 (09:55 +0200)
commit868b70b9e6bd8d211cb846ad332c777591b68c8f
tree87111053822ccf9effa127914eca5606a70113d0tree | snapshot
parent5fe60d3b680106109fd5c8b5270ef83f076b0c65commit | diff
MIPS: DTS: CI20: Parent MSCMUX clock to MPLL

This makes it possible to clock the SD cards much higher, as the MPLL is
running at 1.2 GHz by default. The previous parent was the EXT clock,
which caused the SD cards to be clocked at 24 MHz maximum.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/boot/dts/ingenic/ci20.dts diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git