drm/i915/mtl: Use port clock compatible numbers for C20 phy
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Thu, 7 Dec 2023 22:10:23 +0000 (14:10 -0800)
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Fri, 8 Dec 2023 18:59:51 +0000 (10:59 -0800)
commit877fd09a120d0acee073fbada79fad2ab35396c2
tree5d488d26d0338a92adb53803b30663639fc17a62
parentc6117b33a173717714a8dbbf9d14ca85db79725e
drm/i915/mtl: Use port clock compatible numbers for C20 phy

In C20 pll_state link_bit_rate and clock fields are bit redundant. Since
many of the helpers assume the clock values, which are different from
link_bit_rate for dp2.0, convert the helpers to use the numbers that
are compatible with link_bit_rate.

Currently link_bit_rate is compatible with crtc_state->port_clock. The
function intel_c20pll_calc_port_clock returns the number which is
compatible with crtc_state->port_clock. In order to avoid extra
conversions b/ween clock and link_bit_rate, remove "clock" field from the
C20 pll_state and then rename "link_bit_rate" as "clock".

While at it rely on crtc_state->port_clock during C20 Pll programming.

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231207221025.2032207-2-radhakrishna.sripada@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c