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(parent: 8406d19) | patch
dt-bindings: riscv: Add SiFive S7 compatible
authorHal Feng <hal.feng@starfivetech.com>
Sat, 1 Apr 2023 11:19:30 +0000 (19:19 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 5 Apr 2023 14:50:11 +0000 (15:50 +0100)
commit8868caa2a073cdac8a3c28e4e30cf72fe6b44f22
treef15321ef48adfba80be82ad97a5670547bc0624atree | snapshot
parent8406d19ca0493aa8b4b83314efe57219c8bb92b6commit | diff
dt-bindings: riscv: Add SiFive S7 compatible

Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/riscv/cpus.yaml diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git