clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 30 Aug 2019 13:45:12 +0000 (15:45 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 1 Oct 2019 08:24:55 +0000 (10:24 +0200)
commit8a6d97a46dfd73a87b76a277b2045bd4036c35aa
treec9e8626ec6deb4149f5d50ab2918d0c7cbd1afad
parentf1195d4ec70b230553bbab80c251c3cd79db715b
clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()

cpg_sd_clock_round_rate() really needs the best rate, not the best
divider.  Hence change the iteration to find the former, and get rid of
the final division.

Add an out-of-range rate check while at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-6-geert+renesas@glider.be
drivers/clk/renesas/rcar-gen3-cpg.c