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clk: samsung: add BPLL rate table for Exynos 5422 SoC
authorLukasz Luba <l.luba@partner.samsung.com>
Wed, 5 Jun 2019 16:54:00 +0000 (18:54 +0200)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 6 Jun 2019 13:53:10 +0000 (15:53 +0200)
commit8b4a7acf7b30c811c5cd8b70b615ca8f9efe86cc
tree13d6ad8fe81506c804a20622d3622a426a902b69tree | snapshot
parentcc9bdecf4b8d20b3d3d0f8a6cb3e577548b5539fcommit | diff
clk: samsung: add BPLL rate table for Exynos 5422 SoC

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git