cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
authorRobert Richter <rrichter@amd.com>
Wed, 18 Oct 2023 17:17:00 +0000 (19:17 +0200)
committerDan Williams <dan.j.williams@intel.com>
Sat, 28 Oct 2023 03:13:37 +0000 (20:13 -0700)
commit8ce520fdea245c9e17ebc0659973984362bc1fde
treebb37fdc716e7beadf0177d6c6804ffa2effa7b19
parent2dd18279202f6247904e6e23738c1ec6a86b24b1
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability

Now, that the Component Register mappings are stored, use them to
enable and map the HDM decoder capabilities. The Component Registers
do not need to be probed again for this, remove probing code.

The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
Endpoint's component register mappings are located in the cxlds and
else in the port's structure. Duplicate the cxlds->reg_map in
port->reg_map for endpoint ports.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
[rework to drop cxl_port_get_comp_map()]
Link: https://lore.kernel.org/r/20231018171713.1883517-8-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/hdm.c
drivers/cxl/core/port.c
drivers/cxl/mem.c