hw/riscv: Use error_fatal for SoC realisation
authorAlistair Francis <alistair.francis@wdc.com>
Wed, 5 Jan 2022 21:39:36 +0000 (07:39 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:09 +0000 (15:46 +1000)
commit8f972e5b4beeeb35b15f75499d18a8cc5a320ce7
treec161e5404d32d11b76b14461aa6da554d2a5bde6
parent07cb270a9ac914431577321b0e3e99d79cf56254
hw/riscv: Use error_fatal for SoC realisation

When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.

Currently a user can see this:

   $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash
    QEMU 6.1.93 monitor - type 'help' for more information
    (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229:
    qemu-system-riscv64: OTP drive size < 16K
    Aborted (core dumped)

Which this patch addresses

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
hw/riscv/microchip_pfsoc.c
hw/riscv/opentitan.c
hw/riscv/sifive_e.c
hw/riscv/sifive_u.c