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(parent: 8f3d9f3) | patch
CLK: HSDK: CGU: check if PLL is bypassed first
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 11 Mar 2020 13:41:13 +0000 (16:41 +0300)
committerStephen Boyd <sboyd@kernel.org>
Fri, 29 May 2020 04:06:39 +0000 (21:06 -0700)
commit907f9291f937463c27e5ca9cb5f1d8eedf9a2738
tree81d08faa17508d4a678aef95d518dcfe3290f5bbtree | snapshot
parent8f3d9f354286745c751374f5f1fcafee6b3f3136commit | diff
CLK: HSDK: CGU: check if PLL is bypassed first

If PLL is bypassed the EN (enable) bit has no effect on
output clock.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-2-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-hsdk-pll.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git