clk: tegra: pll: Add pre/post rate-change hooks
authorDmitry Osipenko <digetx@gmail.com>
Thu, 19 Mar 2020 19:02:19 +0000 (22:02 +0300)
committerThierry Reding <treding@nvidia.com>
Tue, 12 May 2020 20:48:42 +0000 (22:48 +0200)
commit9157abe74b05b9c2ede8f07ad4c7f89b717ff303
treed560cd35b479e4b62a427548eb06a05f2a571922
parent1641567920fc363be971f9059f3e7afc58a0dda6
clk: tegra: pll: Add pre/post rate-change hooks

There is a need to temporarily re-parent CCLK away from PLLX if PLLX's
rate is about to change. The newly introduced PLL pre/post rate-change
hooks allow to handle such case.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c
drivers/clk/tegra/clk.h