drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
authorGustavo Sousa <gustavo.sousa@intel.com>
Tue, 12 Mar 2024 16:36:36 +0000 (13:36 -0300)
committerLucas De Marchi <lucas.demarchi@intel.com>
Wed, 13 Mar 2024 12:46:45 +0000 (05:46 -0700)
commit9161e31181440e4882f78e02783e40325dc82e27
tree102405788edd42d5a73fb50384610576d63ff22c
parent66a0e0681392420b326f00ba732e6bda099eda29
drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state

Xe2LPD always selects the CDCLK PLL as source for the MDCLK. Because of
that, the ratio between MDCLK and CDCLK is not be constant anymore. As
such, make sure to have the current ratio available in intel_dbuf_state
so that it can be used during dbuf programming.

Note that we write-lock the global state instead of serializing to a
hardware commit because a change in the ratio should be rather handled
in the CDCLK change sequence, which will need to take care of updating
the necessary registers in that case. We will implement that in upcoming
changes.

That said, changes in the MBus joining state should be handled by the
DBUF/MBUS logic, just like it is already done, but the logic will need
to know the ratio to properly update the registers.

v2:
  - Make first sentence of commit message more intelligible. (Matt)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240312163639.172321-6-gustavo.sousa@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c
drivers/gpu/drm/i915/display/intel_cdclk.h
drivers/gpu/drm/i915/display/skl_watermark.c
drivers/gpu/drm/i915/display/skl_watermark.h