target/riscv: Allow users to force enable AIA CSRs in HART
authorAnup Patel <anup.patel@wdc.com>
Fri, 4 Feb 2022 17:46:53 +0000 (23:16 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:19 +0000 (12:24 +1000)
commit91870b510ae5d1cb9688231b8f01dceaab64de68
treeba65ce0852fb058178a1cdd33194cf1879276718
parentd207863cd3ed056055e2324a4abe47f54e7c6384
target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h