target/riscv: Move Guest irqs out of the core local irqs range.
authorRajnesh Kanwal <rkanwal@rivosinc.com>
Mon, 20 May 2024 12:51:57 +0000 (13:51 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 12:29:17 +0000 (22:29 +1000)
commit92c82a126e633c51ac01b6fc158123aca96dddf6
treefdc5d652a92e21f9a1215936e8477d4dd5e64a3c
parent87088fadb352c1ffa8718015f25564fc64079f4e
target/riscv: Move Guest irqs out of the core local irqs range.

Qemu maps IRQs 0:15 for core interrupts and 16 onward for
guest interrupts which are later translated to hgiep in
`riscv_cpu_set_irq()` function.

With virtual IRQ support added, software now can fully
use the whole local interrupt range without any actual
hardware attached.

This change moves the guest interrupt range after the
core local interrupt range to avoid clash.

Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.")
Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.")
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240520125157.311503-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h
target/riscv/csr.c