dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
authorInochi Amaoto <inochiama@outlook.com>
Wed, 4 Oct 2023 15:43:47 +0000 (23:43 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Fri, 6 Oct 2023 13:40:09 +0000 (14:40 +0100)
commit942e02e150721413b43068a8073819ad2b7d6314
tree012019fe3d19745ee3b31cc2201c01ad62fcccce
parent4734449f73115c33733b136e225657107c03faf5
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and
implements the not yet frozen ACLINT spec. This spec seems to be
abandoned, and will not be frozen in the predictable future.
Frozen specs required by the RISC-V maintainers before merging content
relating to those extensions, therefore a generic compatible is not
appropriate.
Instead, add new vendor specific compatible strings to identify mswi of
sg2042 clint.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[conor: re-wrote commit message to drop irrelevant sifive,clint discussion]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml [new file with mode: 0644]