riscv: move the TLB flush logic out of line
authorChristoph Hellwig <hch@lst.de>
Wed, 21 Aug 2019 14:58:37 +0000 (23:58 +0900)
committerPaul Walmsley <paul.walmsley@sifive.com>
Thu, 5 Sep 2019 08:54:51 +0000 (01:54 -0700)
commit95594cb40c6e013e04659f7316fbdebe83913c58
treec76bb919d36e75cd7e1fb77d585665284694dca4
parent2f12dbf190d97dc0f2f8a07269dd0d8060808539
riscv: move the TLB flush logic out of line

The TLB flush logic is going to become more complex.  Start moving
it out of line.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
[paul.walmsley@sifive.com: fixed checkpatch whitespace warnings]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
arch/riscv/include/asm/tlbflush.h
arch/riscv/mm/Makefile
arch/riscv/mm/tlbflush.c [new file with mode: 0644]