clk: renesas: r9a07g043: Add support for RZ/Five SoC
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 22 Jun 2022 18:17:23 +0000 (19:17 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 5 Jul 2022 07:20:34 +0000 (09:20 +0200)
commit95d48d270305ad2ce4e6e8d84a9fb6ea49d6f8aa
treefb3a85cd4c470c1a9ee96d12ba63693b54a3c12c
parentce05f30dc3a04ca32f91f9fd2a3de7e0b52b0417
clk: renesas: r9a07g043: Add support for RZ/Five SoC

Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for
RZ/Five SoC.

This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five
SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220622181723.13033-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c