target/riscv: Implement Ssdbltrp exception handling
authorClément Léger <cleger@rivosinc.com>
Fri, 10 Jan 2025 12:54:35 +0000 (13:54 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:35 +0000 (09:44 +1000)
commit967760f62c7ca5ab6194131f4ff152b37f2d7017
tree6745b819929a3c81068cec40bb3d69756a0f438a
parent72d71d87327f47dc878683f4ff6a21472d5dcfdc
target/riscv: Implement Ssdbltrp exception handling

When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-5-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c