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(parent: f671d11) | patch
drm/i915: Limit FBC flush to post batch flush
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 6 Nov 2013 21:02:19 +0000 (23:02 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 21 Nov 2013 08:06:09 +0000 (09:06 +0100)
commit9688ecadd268770834cca72ac81c9aec8fb8cf2f
tree59873979bde7ea17153fc768604fb36a793b154ctree | snapshot
parentf671d117bc0338b67b0a7485882d332fe6c4b570commit | diff
drm/i915: Limit FBC flush to post batch flush

Don't issue the FBC nuke/cache clean command when invalidate_domains!=0.
That would indicate that we're not being called for the post-batch
flush.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git