pinctrl: cy8c95x0: Add reset support
authorPatrick Rudolph <patrick.rudolph@9elements.com>
Fri, 14 Jul 2023 08:19:01 +0000 (10:19 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Thu, 20 Jul 2023 19:18:21 +0000 (21:18 +0200)
commit99084881de88ffcd156b03aaeb7d4eb740005e3e
treec7e7aa4ea7d546bf4342c15329e2122cc364bf92
parenta4f1d0dd9bd153ef5d326ad040c47f0a909361ca
pinctrl: cy8c95x0: Add reset support

This patch adds support for an optional "reset" GPIO pin in the cy8c95x0
pinctrl driver. On probe, the reset pin is pulled low to bring chip out
of reset. The reset pin has an internal pull-down and can be left
floating if not required.

The datasheet doesn't mention any timing related to the reset pin.

Based on empirical tests, it was found that the chip requires a
delay of 250 milliseconds before accepting I2C transfers after driving
the reset pin low. Therefore, a delay of 250ms is added before
proceeding with I2C transfers.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Link: https://lore.kernel.org/r/20230714081902.2621771-2-Naresh.Solanki@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/pinctrl-cy8c95x0.c