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(parent: 25e168a) | patch
target/arm: read access to performance counters from EL0
authorAlex Zuepke <alex.zuepke@tum.de>
Thu, 28 Apr 2022 13:27:17 +0000 (15:27 +0200)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 5 May 2022 08:36:22 +0000 (09:36 +0100)
commit99a50d1a67c602126fc2b3a4812d3000eba9bf34
treed9c884c619ccfdae3c8e38764d50c28591ce894ctree | snapshot
parent25e168ab70627bf3368944cf5b1d97490c853007commit | diff
target/arm: read access to performance counters from EL0

The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.

Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper.c diff | blob | history
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