projects / qemu.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 53677ac) | patch
target/riscv: Create RISCVMXL enumeration
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 20 Oct 2021 03:16:56 +0000 (20:16 -0700)
committerAlistair Francis <alistair@alistair23.me>
Thu, 21 Oct 2021 21:47:51 +0000 (07:47 +1000)
commit99bc874fb3a0709c36ae4e594a1262ce1660e698
treec1f5ff95c30c2f77366d73413d4e5836fecd4e1dtree | snapshot
parent53677acf25afa8e529d7f81a6ae9a03d15c72713commit | diff
target/riscv: Create RISCVMXL enumeration

Move the MXL_RV* defines to enumerators.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.