clk: renesas: r8a779f0: Add SDH0 clock
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Mon, 11 Jul 2022 13:46:54 +0000 (15:46 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 Aug 2022 09:08:54 +0000 (11:08 +0200)
commit9b5dd1ff705c68549f7a2a91dd8beee14bc543e1
tree888a3f5c6c7e1fa9538d4c78cce0236ac2f52abf
parent568035b01cfb107af8d2e4bd2fb9aea22cf5b868
clk: renesas: r8a779f0: Add SDH0 clock

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220711134656.277730-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a779f0-cpg-mssr.c