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clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
authorTaniya Das <tdas@codeaurora.org>
Mon, 11 Feb 2019 07:39:28 +0000 (13:09 +0530)
committerStephen Boyd <sboyd@kernel.org>
Thu, 21 Feb 2019 22:18:13 +0000 (14:18 -0800)
commit9d575719ca9b8e177391addb2855be3911dc0d93
tree67eb504d8ef11b8d81b29922136c9f61c810c9b4tree | snapshot
parent96dc791d0b9e12f6374a80f00ad9304b9df2efeecommit | diff
clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/qcom/gcc-qcs404.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git