RISC-V: Detect Smstateen extension
authorMayuresh Chitale <mchitale@ventanamicro.com>
Wed, 13 Sep 2023 16:38:59 +0000 (22:08 +0530)
committerAnup Patel <anup@brainfault.org>
Thu, 12 Oct 2023 13:03:27 +0000 (18:33 +0530)
commit9dbaf381008dfa2fad6225633004f7adb1bac252
treeb0ecd83778851aaf7eeafdc3a7b3f8a29629f851
parent94f6f0550c625fab1f373bb86a6669b45e9748b3
RISC-V: Detect Smstateen extension

Extend the ISA string parsing to detect the Smstateen extension. If the
extension is enabled then access to certain 'state' such as AIA CSRs in
VS mode is controlled by *stateen0 registers.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpufeature.c