dt-bindings: riscv: Add Andes AX45MP core to the list
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 28 Oct 2022 16:59:16 +0000 (17:59 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 10 Nov 2022 14:59:03 +0000 (15:59 +0100)
commit9f643dc28e2c072d7d323898530ee37433e74595
treecbe572bef22696282e0248d201a5eec881a35735
parent57e1b873c2f54253f4c81bddb782e183ee6544ae
dt-bindings: riscv: Add Andes AX45MP core to the list

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.

More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Documentation/devicetree/bindings/riscv/cpus.yaml