net/cadence_gem: Implement SAR match bit in rx desc
authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Wed, 4 Dec 2013 05:57:59 +0000 (21:57 -0800)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 10 Dec 2013 13:28:50 +0000 (13:28 +0000)
commita03f742983f9b6ed03913b30005b6f053290d285
treed15a4ba905efa362779c69fe9cfe5ecb03bd660f
parent63af1e0cff8879a3ddd1b08abb3172b49fb88c88
net/cadence_gem: Implement SAR match bit in rx desc

Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.

This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware.

Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 7e3f26fc4ab244e8123efc12723e7164730abdcb.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/net/cadence_gem.c