dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 13 Jul 2023 11:38:58 +0000 (19:38 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:08:00 +0000 (18:08 +0100)
commita097a5ec14dff59568b1e6c8bd8cc37a21d8811f
treeefb36e0ae95e319985148b93dac7c3d888e8c30a
parent9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml [new file with mode: 0644]
include/dt-bindings/clock/starfive,jh7110-crg.h
include/dt-bindings/reset/starfive,jh7110-crg.h