riscv: Add semihosting support
authorKeith Packard <keithp@keithp.com>
Fri, 8 Jan 2021 22:42:52 +0000 (22:42 +0000)
committerAlex Bennée <alex.bennee@linaro.org>
Mon, 18 Jan 2021 10:05:06 +0000 (10:05 +0000)
commita10b9d93ecea0a8f01eb6de56274b1bcb101083b
tree24d8b952a691501fa22791881425539e33535d5a
parent095f8c029319b79cce487e3b566cd826b93da3e6
riscv: Add semihosting support

Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in

   https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210107170717.2098982-6-keithp@keithp.com>
Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
13 files changed:
default-configs/devices/riscv32-softmmu.mak
default-configs/devices/riscv64-softmmu.mak
default-configs/targets/riscv32-linux-user.mak
default-configs/targets/riscv64-linux-user.mak
hw/semihosting/arm-compat-semi.c
hw/semihosting/common-semi.h
linux-user/qemu.h
linux-user/semihost.c
qemu-options.hx
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c
target/riscv/insn_trans/trans_privileged.c.inc
target/riscv/translate.c