Hexagon: fix HVX store new
authorMatheus Tavares Bernardino <quic_mathbern@quicinc.com>
Mon, 20 May 2024 15:53:04 +0000 (12:53 -0300)
committerBrian Cain <bcain@quicinc.com>
Sun, 9 Jun 2024 00:48:50 +0000 (17:48 -0700)
commita1852002c7509569eaaedb783925f34350fe0a84
treea7112e5376213556df5e9d425a11180dd75d88fa
parent3e246da2c3f85298b52f8a1154b832acf36aa656
Hexagon: fix HVX store new

At 09a7e7db0f (Hexagon (target/hexagon) Remove uses of
op_regs_generated.h.inc, 2024-03-06), we've changed the logic of
check_new_value() to use the new pre-calculated
packet->insn[...].dest_idx instead of calculating the index on the fly
using opcode_reginfo[...]. The dest_idx index is calculated roughly like
the following:

    for reg in iset[tag]["syntax"]:
        if reg.is_written():
            dest_idx = regno
            break

Thus, we take the first register that is writtable. Before that,
however, we also used to follow an alphabetical order on the register
type: 'd', 'e', 'x', and 'y'. No longer following that makes us select
the wrong register index and the HVX store new instruction does not
update the memory like expected.

Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Message-Id: <f548dc1c240819c724245e887f29f918441e9125.1716220379.git.quic_mathbern@quicinc.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
target/hexagon/gen_trans_funcs.py
tests/tcg/hexagon/hvx_misc.c