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usb: chipidea: tegra: Specify TX FIFO threshold in UDC SoC info
authorDmitry Osipenko <digetx@gmail.com>
Fri, 18 Dec 2020 12:02:44 +0000 (15:02 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 13 Jan 2021 10:26:34 +0000 (11:26 +0100)
commita1fdd107cd0c7cf3a575c994cc2766c67b6689e0
tree0135199cae5ed47bc78b0ec173b2ac462ea81948tree | snapshot
parenta728f91bcc70dc9c7f50ac25a37806c0bbb7108bcommit | diff
usb: chipidea: tegra: Specify TX FIFO threshold in UDC SoC info

The UDC/OTG controller could be switched to a host mode and the
TXFILLTUNING register needs to be programmed properly for the host
mode. Hence specify the TX FIFO threshold in the UDC SoC info.

Acked-by: Peter Chen <peter.chen@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201218120246.7759-8-digetx@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/chipidea/ci_hdrc_tegra.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git