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Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
authorTaylor Simpson <tsimpson@quicinc.com>
Mon, 10 Apr 2023 16:09:41 +0000 (09:09 -0700)
committerTaylor Simpson <tsimpson@quicinc.com>
Fri, 21 Apr 2023 16:32:52 +0000 (09:32 -0700)
commita305a170398d80c08e19c2ef4c8637a4f4de50e1
treedab4ac994cd1ca8a5c528e0034d6544926ff0d97tree | snapshot
parent111c529aa652fde71fe54a91776ffd166b724b42commit | diff
Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions

Most of these are not modelled in QEMU, so save the overhead of
calling a helper.

The only exception is dczeroa.  It assigns to hex_dczero_addr, which
is handled during packet commit.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
target/hexagon/gen_tcg.h diff | blob | history
target/hexagon/macros.h diff | blob | history
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