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clk: renesas: r8a779g0: Add watchdog clock
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 9 Sep 2022 09:25:12 +0000 (11:25 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Sun, 18 Sep 2022 12:43:51 +0000 (14:43 +0200)
commita4f8a6e60cd54073d27c857cd0c659c5c79cebe2
treeb11b9a8ab787399126a946d1e379b581953280f1tree | snapshot
parente312ae92077f90d6ccdca05fb6d640bd9624c37ccommit | diff
clk: renesas: r8a779g0: Add watchdog clock

Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
drivers/clk/renesas/r8a779g0-cpg-mssr.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git