target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)
authorRichard Henderson <richard.henderson@linaro.org>
Sat, 1 Feb 2025 16:39:54 +0000 (16:39 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 11 Feb 2025 16:22:07 +0000 (16:22 +0000)
commita66c4585fff70ffc4a61e0f5f5528320a55cd9cd
tree8c170182fb82cf4d6236055d5e71ee1e4e69eeba
parentf67a16e7d754cde9a55dd1e26ea4db48701b6fb9
target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)

Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.

Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need toa pass in the
FPCR.AH value via the SIMD data word.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250129013857.135256-33-richard.henderson@linaro.org
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/tcg/vec_helper.c