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hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
authorAlistair Francis <alistair.francis@wdc.com>
Mon, 30 Aug 2021 05:34:36 +0000 (15:34 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Sep 2021 21:56:49 +0000 (07:56 +1000)
commita714b8aa029c2a6cc0b99a798f4f8b6d4282e711
tree90c3c011b203b8e9f7d05b473c3b6101c0f2f209tree | snapshot
parent0f0b70eeecdd4e0f29efe28a7ffec01cbe5c43bfcommit | diff
hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com
hw/intc/sifive_clint.c diff | blob | history
include/hw/intc/sifive_clint.h diff | blob | history
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