hw/riscv/riscv-iommu: add DBG support
authorTomasz Jeznach <tjeznach@rivosinc.com>
Wed, 16 Oct 2024 20:40:34 +0000 (17:40 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 31 Oct 2024 03:51:24 +0000 (13:51 +1000)
commita7aa525b93c3f7a847cd2185b71aef97a17ec3d5
tree87626293935fac26df9bc33be73c5414f9641c4e
parent69a9ae483696e185889edaeddacf46afd9110bc6
hw/riscv/riscv-iommu: add DBG support

DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.

The DBG cap is always enabled. No on/off toggle is provided for it.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241016204038.649340-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/riscv-iommu-bits.h
hw/riscv/riscv-iommu.c