riscv: fpu: drop SR_SD bit checking
authorAndy Chiu <andy.chiu@sifive.com>
Mon, 15 Jan 2024 05:59:25 +0000 (05:59 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 16 Jan 2024 15:13:58 +0000 (07:13 -0800)
commita93fdaf183125fea81f66b9bd756ef5a0c30859e
tree925d506ca51e1423243a3e379a52f34a00881621
parentc2a658d419246108c9bf065ec347355de5ba8a05
riscv: fpu: drop SR_SD bit checking

SR_SD summarizes the dirty status of FS/VS/XS. However, the current code
structure does not fully utilize it because each extension specific code
is divided into an individual segment. So remove the SR_SD check for
now.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Song Shuai <songshuaishuai@tinylab.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240115055929.4736-7-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/switch_to.h