tools/power/turbostat: Simplify the logic for RAPL enumeration
authorZhang Rui <rui.zhang@intel.com>
Sat, 26 Aug 2023 06:57:12 +0000 (14:57 +0800)
committerZhang Rui <rui.zhang@intel.com>
Wed, 27 Sep 2023 14:14:19 +0000 (22:14 +0800)
commita98f886035d5f7e0ec66036dd6bf98b40e75b692
tree1b91f7e7410926142319cee30196612ca56e96da
parentb9cd66833d3a651cea10666674e9abcf2182e8ad
tools/power/turbostat: Simplify the logic for RAPL enumeration

The support for each RAPL domains, as well as the support for the perf
status of each RAPL domains, can be detected by checking the
availabilities of the corresponding RAPL MSRs.

Change the code accordingly and remove the hardcoded logic for each
model.

Note that this also fixes the INTEL_FAM6_ATOM_TREMONT model, which has
RAPL_PKG_PERF_STATUS and MSR_DRAM_PERF_STATUS but doesn't have BIC_PKG__
and BIC_RAM__ set.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
tools/power/x86/turbostat/turbostat.c