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LoongArch: Define regular names for BCE/WATCH/HVC/GSPR exceptions
authorWANG Xuerui <git@xen0n.name>
Mon, 1 May 2023 09:19:10 +0000 (17:19 +0800)
committerHuacai Chen <chenhuacai@loongson.cn>
Mon, 1 May 2023 09:19:10 +0000 (17:19 +0800)
commitaa552254cf0039d83908105a07007f9ea616c119
tree27ae8539eec4b6ef4f4c95cfac31f2ec93eff52ctree | snapshot
parent9e36fa42995a7c7fa8d84a429ca647736c4f1c66commit | diff
LoongArch: Define regular names for BCE/WATCH/HVC/GSPR exceptions

Define them according to the ISA manual, in order to enable matching the
sub-exceptions for humanization purposes later.

Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
arch/loongarch/include/asm/loongarch.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git