riscv: Factor out page table TLB synchronization
authorSamuel Holland <samuel.holland@sifive.com>
Wed, 27 Mar 2024 04:49:43 +0000 (21:49 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Mon, 29 Apr 2024 17:49:25 +0000 (10:49 -0700)
commitaaa56c8f378dd798f4a7f633cbf2eb129e98e6a4
tree5c910bc75769690d20f15587d91c780ec8028bba
parent58661a30f1bcc748475ffd9be6d2fc9e4e6be679
riscv: Factor out page table TLB synchronization

The logic is the same for all page table levels. See commit 69be3fb111e7
("riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU").

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240327045035.368512-3-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/pgalloc.h