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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
authorStephen Warren <swarren@nvidia.com>
Wed, 23 Jan 2013 16:43:49 +0000 (09:43 -0700)
committerStephen Warren <swarren@nvidia.com>
Mon, 28 Jan 2013 18:24:09 +0000 (11:24 -0700)
commitabf80c276dca1bf40b342b4ebf7815be0f6ba564
tree4b90282b64e4f0b74200c120c96206c052dd6dfatree | snapshot
parentbf5fcc76d31418950b214542440d5de6e48c7998commit | diff
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi

No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra30-beaver.dts diff | blob | history
arch/arm/boot/dts/tegra30-cardhu.dtsi diff | blob | history
arch/arm/boot/dts/tegra30.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git