RISC-V: Add support for vectored interrupts
authorMichael Clark <mjc@sifive.com>
Sat, 16 Mar 2019 01:21:03 +0000 (01:21 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 19 Mar 2019 12:14:39 +0000 (05:14 -0700)
commitacbbb94e5730c9808830938e869d243014e2923a
tree3398a36b64ab9b9e50e6b7907e81d5b49dbf6595
parentd26f5a423438e579d3ff0ca35e44edb966a36233
RISC-V: Add support for vectored interrupts

If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

 pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu_helper.c
target/riscv/csr.c