drm/amd/display: 3.2.220
authorAric Cyr <aric.cyr@amd.com>
Mon, 16 Jan 2023 04:21:20 +0000 (23:21 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 24 Jan 2023 18:26:26 +0000 (13:26 -0500)
commitacd82cb42bd7cbffeaab15818b4334159b6f6e5a
tree87f8c9fcdd0506c23d6adcb36e2f4ee86473cbdf
parent0f5f1ee45ff8e76916be2290ef91cc2234450ccb
drm/amd/display: 3.2.220

This version brings along following fixes:
- Fix timing not changning when freesync video is enabled
- avoid disable otg when dig was disabled
- Properly reuse completion structure
- Pass DSC slice height to PSR FW
- merge dc_link_dp into dc_link
- move dp cts functions from dc_link_dp to link_dp_cts
- move dp irq handler functions from dc_link_dp to link_dp_irq_handler
- Enable AdaptiveSync in DC interface
- adjust MALL size available for DCN32 and DCN321
- Set init freq for DCFCLK DS
- Use |= when assigning wm_optimized_required
- move eDP panel control logic to link_edp_panel_control
- create accessories, hwss and protocols sub folders in link
- Disable SubVP for PSR panels

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dc.h