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(parent: ca0e5d8) | patch
target-mips: update mips32r5-generic into P5600
authorYongbok Kim <yongbok.kim@imgtec.com>
Fri, 10 Jul 2015 11:10:52 +0000 (12:10 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Thu, 13 Aug 2015 15:21:12 +0000 (16:21 +0100)
commitaff2bc6dc6d839caf6df0900437cc2cc9e180605
tree36c2a96d9ca4eb179a8d2256a1a071317b0e8470tree | snapshot
parentca0e5d8b0d065a95d0f9042f71b2ace45b015596commit | diff
target-mips: update mips32r5-generic into P5600

As full specification of P5600 is available, mips32r5-generic should
be renamed to P5600 and corrected as its intention.
Correct PRid and detail of configuration.
Features which are not currently supported are described as FIXME.

Fix Config.MM bit location

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: correct cache line sizes and LLAddr shift]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/cpu.h diff | blob | history
target-mips/translate_init.c diff | blob | history
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