arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC
authorSinthu Raja <sinthu.raja@ti.com>
Thu, 21 Sep 2023 10:00:37 +0000 (15:30 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 5 Oct 2023 15:14:41 +0000 (20:44 +0530)
commitb024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb
treee21039481290a9903fa098bf9961fb5452dfcb2e
parentc2e7258dbd451fff84fac2375aaec2f56f57f0b3
arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC

Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap. Update the macro definition for it.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921100039.19897-2-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-serdes.h