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clk: tegra: dfll: registration for multiple SoCs
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Fri, 4 Jan 2019 03:06:47 +0000 (11:06 +0800)
committerThierry Reding <treding@nvidia.com>
Wed, 6 Feb 2019 13:28:25 +0000 (14:28 +0100)
commitb0dcfb78dc6aec8698ab5900dfdf6aeae0830815
tree7c5fa38f885fc0ae83c1d8f944a0745f90f45bb1tree | snapshot
parentbfeffd155283772bbe78c6a05dec7c0128ee500ccommit | diff
clk: tegra: dfll: registration for multiple SoCs

In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git