drm/i915/gt: Update RC6 mask for mtl_drpc
authorBadal Nilawar <badal.nilawar@intel.com>
Wed, 20 Sep 2023 09:06:20 +0000 (14:36 +0530)
committerAnshuman Gupta <anshuman.gupta@intel.com>
Thu, 21 Sep 2023 11:15:07 +0000 (16:45 +0530)
commitb17e6840882dc8a04e7464270906d79954378d41
tree50765bb60ab06014a3c6f4811f5e31869dda88ef
parent26a8e32e6d77900819c0c730fbfb393692dbbeea
drm/i915/gt: Update RC6 mask for mtl_drpc

It has been observed sometimes RC6 status register's unused bits are
being set by h/w, without affecting RC6 functionality therefore updating
the mask with used bits accordingly.
As mtl_drpc is debugfs function, removing MISSING_CASE from default case as
it doesn't make sense to panic (panic_on_warn=1) the CI system if register
is reporting unsupported state.

Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230920090620.3255091-1-badal.nilawar@intel.com
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
drivers/gpu/drm/i915/gt/intel_gt_regs.h